Higher-Density Data Storage

A novel nanolaser could cram more data onto a hard disk.

By Prachi Patel-Predd

Spot light: To make a laser that focuses nanowatts of power into a 30-nanometer spot, researchers cover a semiconductor diode with an aluminum film etched with different nanoscale apertures. A scanning near-field optical-microscope image shows that the most laser light comes out from the C-shaped aperture. Credit: Rabee Ikkawi, University of California, Riverside

A laser that focuses light into a 30-nanometer-wide spot could be an important advance toward ultra-high-density hard disks. Researchers at the University of California, Riverside (UCR), and at the University of Houston, in Texas, who have developed the nanolaser, say that it could lead to hard disks with 10 terabits of data packed into a square inch.

Today, hard disks can carry up to 200 gigabits per square inch. Data is stored magnetically. Using existing technology, manufacturers could increase a disk's capacity to at most one terabit per square inch. The nanolaser is an important step toward a disk-writing system that many researchers are currently working on. Such a system would use both light and magnetic fields to store data on a disk, packing up to 50 terabits per square inch of data.

The smaller the light spot of the laser, the smaller the bit size, which means more bits per square inch. Right now, the laser can concentrate 250 nanowatts of power on a 30-nanometer-wide spot. "Our technology can be scaled down to 5 to 10 nanometers for sure," says Sakhrat Khizroev, an electrical-engineering professor who is leading the work at UCR. A 10-nanometer spot size should be small enough to get a density of 10 terabits per square inch.

Present-day magnetic storage technology has doubled data density on hard disks nearly every year for the past three decades. But now the technology is approaching its limit. On a hard disk, each bit is a tiny area in which the material's crystals all have their magnetic fields aligned in the same direction. As more data is recorded on a disk, bits get smaller and comprise fewer crystals of the material. At about one terabit per square inch, the bit areas become so tiny that the crystals do not have enough energy to keep their magnetic fields aligned, and the bits end up losing their information.

Hard-disk manufacturers such as Seagate are now looking at a new method to store more data on disks. The technique, called heat-assisted magnetic recording, involves using a tightly focused light spot to heat up the bits when they are being recorded. This gives the magnetic crystals energy to retain their magnetic-field orientations. "There are various ways one could imagine bringing light on the disk," says Mark Kryder, an electrical- and computer-engineering professor at Carnegie Mellon University. "The most elegant way would be to use a nanolaser."

So far, the challenge has been to make a laser that delivers sufficient energy into a small enough light spot. With previous lasers, Khizroev says, "the light, when focused on a 30-nanometer spot size, has energies that are a fraction of a nanowatt." He and his colleagues make their 250-nanowatt laser by depositing a very thin layer of aluminum on the emitting side of a semiconductor diode laser. Then they focus a beam of positive gallium ions on the aluminum to etch tiny nanoscale apertures. As predicted by physics theory, a C-shaped aperture lets the most energy come through into the smallest spot size. Khizroev says that his colleagues are now trying to engineer the laser with an even smaller spot size of 5 to 10 nanometers.

Ed Schlesinger, head of the Electrical and Computer Engineering department at Carnegie Mellon, says that the new nanolaser is "an important aspect of making heat-assisted magnetic recording a reality." But he cautions that there are many engineering challenges to solve before the technology can be brought to market. They include mounting the laser on a slider so that it can move to various areas of the hard disk to record data, designing a new disk material that works with heat-assisted recording, and making disk lubricants that can handle the high temperatures during the heat-assisted writing process.

"Heat-assisted magnetic recording is a real systems problem and requires development and progress on a lot of fronts simultaneously," Schlesinger says. "The nanolaser is a nice step forward and brings the technology closer."

Researchers Pencil In Graphene Transistors

Graphene's weird electrical properties allow for smallest transistor yet.

IMAGE: Anna Demian/Randi Silberman

Pushing Pencils: Graphene, found in pencil marks, is a candidate material for making future transistors. It's extracted from graphite crystals [right] using sticky tape.

The little smudges you leave behind whenever you use a pencil could be the key ingredient of the next revolution in computer circuitry, according to experts around the globe. Part of what shears off from the graphite in a pencil is a substance known as graphene, a one-atom-thick crystal with remarkable electrical properties that may overcome the physical limits silicon faces as transistors shrink to ever-smaller sizes.

Silicon's remarkable run as ruler of the chip world may be nearing an end as engineers eventually lose the ability to make faster silicon transistors by making them smaller. In the hunt for what comes next, carbon nanotubes have gotten a big chunk of the attention, but if the current explosion of research activity is any indication, it may be graphene that wins in the end. This spring saw a flurry of breakthroughs surrounding graphene, culminating in the creation of what may be the smallest transistor ever made—one atom thick by 10 to 50 atoms wide.

Like carbon nanotubes, graphene is a crystal structure of carbon atoms but arranged in a flat plane instead of a cylinder. The electrons in graphene behave as if they have no mass. Like photons—but unlike electrons in other materials—the electrons move at a constant speed, regardless of how much energy each one has.

A transistor built out of graphene, therefore, should operate much faster than a comparable one made from silicon. Michael S. Fuhrer, a physicist at the University of Maryland's Center for Nanophysics and Advanced Materials, recently showed that at room temperature electrons in graphene move at 200000 centimeters per second for every volt per centimeter of electric field, 100 times faster than in silicon. “All other things being equal, that would translate into a 100 times faster transistor,” he says.

Graphene has been known for decades as a single plane of graphite, but it was only in 2004 that Andre Geim and Kostya Novoselov of the University of Manchester, England, were able to isolate it by the simple act of pressing a piece of tape to a graphite crystal and placing it on a silicon substrate. In April, the two researchers described their transistor, 10 to 50 atoms wide and built by etching a pattern into graphene. [read more]

IBM developing miniature pipes of water for chip cooling

Since a computer microprocessor is veined with electric circuitry, it might seem like a bad place to put water. But IBM Corp. researchers believe that sloshing water through hair-thin pipes inside chips will solve a vexing problem facing next-generation computers.

That problem is heat.

As chips get smaller and smaller, cramming more processing power into ever-tinier spaces, the heat thrown off by the miniature circuits becomes harder to manage. Cooling measures used now to avoid chip meltdowns, including "heat sinks" made from heat-absorbing materials, might not work on tinier scales.

In fact, in a future microprocessor design IBM is exploring -- in which chips are stacked vertically to save space and enhance performance, rather than arrayed next to each other -- the heat-to-volume ratio exceeds that of a nuclear reactor.

To address that, IBM researchers say they could pipe water in between chips that are sandwiched together. The system, which IBM planned to explain Thursday at a technical conference, uses pipes that are just 50 microns wide -- 50 millionths of a meter. The tiny tubes are sealed to prevent leaks and electrical shorts.

Even these micro amounts of water can handle prodigious cooling chores, because water is much more efficient than air at absorbing heat. That is why some high-end computers long have used water cooling. The new trick here is that IBM expects to do it at the miniature scale, inside chips.

"It's never been applied this close to the heart of the matter," said analyst Richard Doherty of the Envisioneering Group.

Yogendra Joshi, an engineering professor at the Georgia Institute of Technology, said aspects of IBM's approach already have been shown by other researchers. But he said the company deserves credit for trying to push the idea toward commercialization.

"There has been a great aversion to piping liquids through electronics," Joshi said. "That's understandable."

However, IBM's tiny pipes aren't out of the lab yet. They're at least five years from becoming available.

[Source: Technology Review, Published by MIT]

The Hunt for the Kill Switch

Are chip makers building electronic trapdoors in key military hardware? The Pentagon is making its biggest effort yet to find out

Last September, Israeli jets bombed a suspected nuclear installation in northeastern Syria. Among the many mysteries still surrounding that strike was the failure of a Syrian radar—supposedly state-of-the-art—to warn the Syrian military of the incoming assault. It wasn't long before military and technology bloggers concluded that this was an incident of electronic warfare—and not just any kind.

Post after post speculated that the commercial off-the-shelf microprocessors in the Syrian radar might have been purposely fabricated with a hidden “backdoor” inside. By sending a preprogrammed code to those chips, an unknown antagonist had disrupted the chips' function and temporarily blocked the radar.

That same basic scenario is cropping up more frequently lately, and not just in the Middle East, where conspiracy theories abound. According to a U.S. defense contractor who spoke on condition of anonymity, a “European chip maker” recently built into its microprocessors a kill switch that could be accessed remotely. French defense contractors have used the chips in military equipment, the contractor told IEEE Spectrum. If in the future the equipment fell into hostile hands, “the French wanted a way to disable that circuit,” he said. Spectrum could not confirm this account independently, but spirited discussion about it among researchers and another defense contractor last summer at a military research conference reveals a lot about the fever dreams plaguing the U.S. Department of Defense (DOD).

Feeding those dreams is the Pentagon's realization that it no longer controls who manufactures the components that go into its increasingly complex systems. A single plane like the DOD's next generation F-35 Joint Strike Fighter, can contain an “insane number” of chips, says one semiconductor expert familiar with that aircraft's design. Estimates from other sources put the total at several hundred to more than a thousand. And tracing a part back to its source is not always straightforward. The dwindling of domestic chip and electronics manufacturing in the United States, combined with the phenomenal growth of suppliers in countries like China, has only deepened the U.S. military's concern.

Recognizing this enormous vulnerability, the DOD recently launched its most ambitious program yet to verify the integrity of the electronics that will underpin future additions to its arsenal. In December, the Defense Advanced Research Projects Agency (DARPA), the Pentagon's R&D wing, released details about a three-year initiative it calls the Trust in Integrated Circuits program. The findings from the program could give the military—and defense contractors who make sensitive microelectronics like the weapons systems for the F‑35—a guaranteed method of determining whether their chips have been compromised. In January, the Trust program started its prequalifying rounds by sending to three contractors four identical versions of a chip that contained unspecified malicious circuitry. The teams have until the end of this month to ferret out as many of the devious insertions as they can.

Vetting a chip with a hidden agenda can't be all that tough, right? Wrong. Although commercial chip makers routinely and exhaustively test chips with hundreds of millions of logic gates, they can't afford to inspect everything. So instead they focus on how well the chip performs specific functions. For a microprocessor destined for use in a cellphone, for instance, the chip maker will check to see whether all the phone's various functions work. Any extraneous circuitry that doesn't interfere with the chip's normal functions won't show up in these tests.

“You don't check for the infinite possible things that are not specified,” says electrical engineering professor Ruby Lee, a cryptography expert at Princeton. “You could check the obvious possibilities, but can you test for every unspecified function?”

[read more]

Post-FET future discussed at IEDM

Silicon-based CMOS FETs will still be used in commercial ICs in twenty years, but it’s likely that completely new devices will also be in production. It seems highly likely that nMOS and pMOS FET “switches” will be used for mainstream logic and memory until 2015-2020, when such things as cross-bar architectures and quantum diodes may be needed. This is the group opinion of the world’s leading IC fab researchers, as discussed in a 2007 IEDM evening panel discussion moderated by Prof. Dimitri Antoniadis of MIT: “Looking Beyond Silicon -- A Pipe Dream or the Inevitable Next Step?”

The industry will reach the practical limits of scaling planar bulk CMOS at different nodes for high-power logic, low-operating power logic, low stand-by power (LSTP) logic, and memory applications. “Transistor pitch scaling will be increasingly difficult due to stronger impact of parasitics and less effective stress engineering. Even if we can do it, power might limit what can be exploited," opined Wilfried Haensch of IBM. Vertical scaling may be required to minimize parasitic capacitance, and high-mobility channel materials must provide the same or better density scaling potential as silicon devices to be attractive. Inherent variability in sub-22nm node devices will be daunting: pattern variation, random discrete dopants, the number of charges per unit device, and interface roughness (poly grain boundaries, high-k morphology, impurity scattering, etc.).

As an example of tough near-term scaling limits, for a physical gate length of 22nm (effective length 16nm), IBM saw that the extrinsic switching time depended upon the current flux through narrow raised source/drain (S/D) regions, with relatively faster switching in short and wide S/D. “There is no new switch in site,” declared Haensch. “All candidates are either non-manufacturable or they can not be wired up.” Lacking a replacement to the silicon FET, system performance will continue to increase with respect to historical trends due to architectural solutions -- i.e., we’ll have systems with many ‘light-weight’ task-specific cores.

Akira Toriumi of the U. of Tokyo gave his educated opinion -- based on first principles of manufacturing he learned at Toshiba -- as to the best directions to go for a post-silicon future. He thinks that silicon microelectronics research will end in 2015, but any new materials, processing, and devices should be simple. “A one-dimension device like a wire, I don’t believe will be a solution; finFET will be a good candidate,” he said. He also advocates the use of germanium instead of compound semiconductors for new channels. “People are talking about Ge for pMOS and III-V for nMOS," he noted, "but why don’t we challenge Ge CMOS? We can get metal S/D Ge nFETs.” For scaling we need to consider not just channel materials but also contact materials for these new channels.

We are now in a world using digital computing solutions that is "very safe and reassuring,” said Jean-Philippe Bourgoin of CEA-LETI. “If we look back at the work of von Neumann and Turing they had to understand the theory much more than we do now.” Audience member Paolo Gargini of Intel interjected that according to the theory of Heisenberg’s Uncertainty principle, Intel’s planned FET scaling will be limited in the year 2020. A member of Gargini’s research group mentioned the crossbar architecture under development in Stan Williams’ Lab at HP as a likely eventual replacement for the FET. (See my Jan. 16, 2007 Ed's Thread for cross-bar architecture and processing details, based on a late 2006 tour of the lab.)

The next afternoon (Session 34, "CMOS Devices -- Advanced Device Structures"), the far limits of CMOS FET technology were shown by Samsung as experimental results of uniaxially strained {110} silicon nanowire transistor (SNWT) channels using an embedded SiGe Source/Drain for greatly improved pMOS performance. Starting with either SOI or bulk silicon wafers, they first grow embedded SiGe (20-40nm thick) and then Si. After hardmask patterning and a clever sequence of etching, the bottom of the grown Si {110} has become SNW floating above the removed SiGe, but the SiGe beneath the S/D remain, and the inherent SiGe/Si lattice-mismatch compressively stresses SNW to provide 1534μA/μm for pMOS. They saw nFET performance only ~15% lower regardless of {110} or {100} orientation, so good overall CMOS results are obtainable using {110}.

Beyond FETs and cross-bar architectures lies a technology concept still mostly disbelieved by the mainstream: quantum electronics. The IEDM plenary session included a talk by Hiroyuki Sakaki, from the Toyota Technological Institute at the U. of Tokyo, on “Roles of Quantum Nanostructures on the Evolution and Future Advances of Electronic and Photonic Devices.” By controlling the electrons within nanoscale layered structures, quantum confinement results in effective two-dimensional electrons and the ability to form devices such as resonant tunneling diodes, quantum wire FETs, quantum dot lasers, and planar superlattice FETs.

However, commercial quantum electronics still remains out in the future. Use of carbon nanotubes (CNT) grown from catalyst particles shows promise, “but it has been very difficult to control the site selection, as well as other parameters,” according to Sakaki. Charge storage phenomena in quantum dots using either Si or InAs appear like the most likely near-term applications. Though if this is merely an extension of flash memory cell technology, does it really count as “quantum electronics?”

In 20 years, will we see a non-FET-based computer? The aggregate opinion seemed to be “yes,” but don’t expect people in the industry who have lived with it forever to be able to think “outside the FET” and develop something revolutionary.