The industry will reach the practical limits of scaling planar bulk CMOS at different nodes for high-power logic, low-operating power logic, low stand-by power (LSTP) logic, and memory applications. “Transistor pitch scaling will be increasingly difficult due to stronger impact of parasitics and less effective stress engineering. Even if we can do it, power might limit what can be exploited," opined Wilfried Haensch of IBM. Vertical scaling may be required to minimize parasitic capacitance, and high-mobility channel materials must provide the same or better density scaling potential as silicon devices to be attractive. Inherent variability in sub-22nm node devices will be daunting: pattern variation, random discrete dopants, the number of charges per unit device, and interface roughness (poly grain boundaries, high-k morphology, impurity scattering, etc.).
As an example of tough near-term scaling limits, for a physical gate length of 22nm (effective length 16nm), IBM saw that the extrinsic switching time depended upon the current flux through narrow raised source/drain (S/D) regions, with relatively faster switching in short and wide S/D. “There is no new switch in site,” declared Haensch. “All candidates are either non-manufacturable or they can not be wired up.” Lacking a replacement to the silicon FET, system performance will continue to increase with respect to historical trends due to architectural solutions -- i.e., we’ll have systems with many ‘light-weight’ task-specific cores.
Akira Toriumi of the U. of Tokyo gave his educated opinion -- based on first principles of manufacturing he learned at Toshiba -- as to the best directions to go for a post-silicon future. He thinks that silicon microelectronics research will end in 2015, but any new materials, processing, and devices should be simple. “A one-dimension device like a wire, I don’t believe will be a solution; finFET will be a good candidate,” he said. He also advocates the use of germanium instead of compound semiconductors for new channels. “People are talking about Ge for pMOS and III-V for nMOS," he noted, "but why don’t we challenge Ge CMOS? We can get metal S/D Ge nFETs.” For scaling we need to consider not just channel materials but also contact materials for these new channels.
We are now in a world using digital computing solutions that is "very safe and reassuring,” said Jean-Philippe Bourgoin of CEA-LETI. “If we look back at the work of von Neumann and Turing they had to understand the theory much more than we do now.” Audience member Paolo Gargini of Intel interjected that according to the theory of Heisenberg’s Uncertainty principle, Intel’s planned FET scaling will be limited in the year 2020. A member of Gargini’s research group mentioned the crossbar architecture under development in Stan Williams’ Lab at HP as a likely eventual replacement for the FET. (See my Jan. 16, 2007 Ed's Thread for cross-bar architecture and processing details, based on a late 2006 tour of the lab.)
The next afternoon (Session 34, "CMOS Devices -- Advanced Device Structures"), the far limits of CMOS FET technology were shown by Samsung as experimental results of uniaxially strained {110} silicon nanowire transistor (SNWT) channels using an embedded SiGe Source/Drain for greatly improved pMOS performance. Starting with either SOI or bulk silicon wafers, they first grow embedded SiGe (20-40nm thick) and then Si. After hardmask patterning and a clever sequence of etching, the bottom of the grown Si {110} has become SNW floating above the removed SiGe, but the SiGe beneath the S/D remain, and the inherent SiGe/Si lattice-mismatch compressively stresses SNW to provide 1534μA/μm for pMOS. They saw nFET performance only ~15% lower regardless of {110} or {100} orientation, so good overall CMOS results are obtainable using {110}.
Beyond FETs and cross-bar architectures lies a technology concept still mostly disbelieved by the mainstream: quantum electronics. The IEDM plenary session included a talk by Hiroyuki Sakaki, from the Toyota Technological Institute at the U. of Tokyo, on “Roles of Quantum Nanostructures on the Evolution and Future Advances of Electronic and Photonic Devices.” By controlling the electrons within nanoscale layered structures, quantum confinement results in effective two-dimensional electrons and the ability to form devices such as resonant tunneling diodes, quantum wire FETs, quantum dot lasers, and planar superlattice FETs.
However, commercial quantum electronics still remains out in the future. Use of carbon nanotubes (CNT) grown from catalyst particles shows promise, “but it has been very difficult to control the site selection, as well as other parameters,” according to Sakaki. Charge storage phenomena in quantum dots using either Si or InAs appear like the most likely near-term applications. Though if this is merely an extension of flash memory cell technology, does it really count as “quantum electronics?”
In 20 years, will we see a non-FET-based computer? The aggregate opinion seemed to be “yes,” but don’t expect people in the industry who have lived with it forever to be able to think “outside the FET” and develop something revolutionary.
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